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Configurable Asynchronous Set/Reset Flip-Flop for Post-Silicon ECOs
Verilog Flip Flop with Enable and Asynchronous Reset - EEWeb
PPT - Chapter 5 Synchronous Sequential Logic 5-1 Sequential Circuits
Edge Triggered D Flip-Flop with Asynchronous Set and Reset Tutorial
Configurable Asynchronous Set/Reset Flip-Flop for Post-Silicon ECOs